>>28111887assign s2_clk = debug_clock;
assign s2_rst = rst1;
assign s2_cyc_i = {m0_adr_o,2'b00} == 32'hF7000000 ? m0_cyc_o : 1'b0;
assign s2_stb_i = m0_stb_o;
assign s2_we_i = m0_we_o;
assign s2_dat_i = m0_dat_o;
assign s2_sel_i = m0_sel_o;
assign s2_err_o = 1'b0;
assign s2_rty_o = 1'b0;
wb_uart uart0 (
.CLK_I (s2_clk),
.RST_I (s2_rst),
.CYC_I (s2_cyc_i),
.STB_I (s2_stb_i),
.SEL_I (s2_sel_i),
.WE_I (s2_we_i),
.DAT_I (s2_dat_i),
.ACK_O (s2_ack_o),
.DAT_O (s2_dat_o),
.RX_I (UART_RX),
.TX_O (UART_TX),
.ISR_O()
