>>1976130RISC-V is objectively inefficient, requiring multiple instructions for what ARM, MIPS, etc. etc. etc. can do in one instruction; just look at those stupid loads of integers.
RISC-V addressing straight up sucks. I'm not asking for much, but at least something like shifted loads would've been a major help there.
No conditional instructions, only branching. adc literally can't exist and that kills bignum performance, which is big for cryptography.
You can't implement multiplication without also having to implement the significantly more complex division because that's how the spec works. Clearly the people who wrote the spec only ever had to make emulators.
Floating point <-> integer register transfers have to go through memory instead of staying in the CPU itself(!).
The encoding for add is the same in the 32 and 64 versions: Unless you know the context it executes in, you don't know if it's 32-bit or 64-bit addition. Instead, 64-bit add.w exists separately, which is counter-intuitive and makes it way harder to create a CPU that works in both 32 and 64 bit modes.
jal also wastes space encoding the link register, which is always going to be one of two in practice anyway.
Fuck RISC-V.
